Single chip processing unit providing immediate availability of frequently used microcode instruction words
US5574883A · kind A · utility
16Cited by
7References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 30, 1993 |
| Grant date | Nov 12, 1996 |
| Priority date | — |
| Expiry date | Nov 30, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/453
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-cache memory system resides on-chip with a system interface to external memory. A general cache memory holds frequently used data and OPCODES for delivery to a processor in one clock cycle. A microcode cache holds frequently used microcode instruction words for delivery to the processor in one clock cycle. Both general and microcode cache memories operate to replace less frequently used OPCODES, data words, and microcode instruction words, with more frequently used words.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.