Processor with sequences of processor instructions for locked memory updates
US5574922A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 17, 1994 |
| Grant date | Nov 12, 1996 |
| Priority date | — |
| Expiry date | Jun 17, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/526
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for executing sequences of instructions which can be used to access a memory location in a locked fashion. The first instruction specifies an address and sets a lock register which disables interrupts until it is cleared. The second instruction specifies an address and clears the lock register. The second instruction is not executed if the lock register was already cleared and doesn't update memory if the cache line of the first address is no longer valid. If the second address is not cacheable, the instructions are off-loaded to the bus interface and the results of the update are used to update the processor state. The present invention allows locked memory updates and process synchronization without locking of arbitrary duration of the entire shared data structure. The calculation and update of the data structure may continue after a context switch. The present invention is compatible with a wide range of cache-coherence protocols.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.