Interconnection process and system for the control of messages in an array of processors having a parallel structure
US5574931A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 1994 |
| Grant date | Nov 12, 1996 |
| Priority date | — |
| Expiry date | Sep 26, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17337
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a process for controlling the circulation of messages in a ring network, in which the data are consecutively supplied, which ensures a consistency of the circulating messages. It also relates to an interconnection system for performing this process. This system comprises a plurality of processors (P0, . . . , Pn) connected on a ring network by means of in each case a cell (C0, . . . , Cn) ensuring the transmission and reception of messages circulating in the ring, a reception module (R0, . . . , Rn) able to store the messages intended for the processor and a transmission module (E0, . . . En) able to store the messages to be supplied to the network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.