System for accessing distributed memory by breaking each accepted access request into series of instructions by using sets of parameters defined as logical channel context
US5574944A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 15, 1993 |
| Grant date | Nov 12, 1996 |
| Priority date | — |
| Expiry date | Dec 15, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A distributed memory I/O interface 10 is provided which allows a plurality of standard peripheral bus I/O controllers 101 to perform multiple transfer operations simultaneously and independently within a networked, distributed memory system 102. The interface 10 includes a peripheral interface 11 to the I/O controllers 101, a memory interface 12 to the distributed memory system 102, a system interface 13 to the processors of the distributed memory system 102, a caching circular buffer RAM 12, and an internal bus 105. The operations of the interface 10 are controlled by logical channels. Each logical channel comprises a channel context, which includes a set of parameters stored in buffer RAM 12 that specify among other things logical address space, a physical memory map, a RAM buffer segment, and a set of allowed transactions for use during channel operations. Data is staged through RAM segments which act as circular buffer caches within the channel's logical address space for sequential transfers, and as doubly-mapped shared memory for random access. The use of an intermediate logically contiguous address space and a caching circular buffer, and the methods by which the parameters …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.