Multi channel inter-processor coupling facility processing received commands stored in memory absent status error of channels
US5574945A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Nov 12, 1996 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0772
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system with a coupling facility is provided with a plurality of processors and a plurality of intersystem channels coupled to the processors via a memory bus. The coupling facility includes a memory bus interface for the memory bus and a plurality of channels for coupling said channels to said processors. The memory bus interface includes an adapter with at least two hardware vectors provided for command detection, command isolation, and parallel testing of the error states of the intersystem channels, one which detects a command vector arrival, and a second which contains error state vector indicators. A LOCATE CHANNEL BUFFER (LCB) instruction is employed which performs a sense and reset operation on the command vector to identify and isolate a new command, and subsequently reads a vector of said error states vector indicator to determine the presence or absence of link errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.