Electronic system including high performance backplane driver/receiver circuits
US5576642A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1995 |
| Grant date | Nov 19, 1996 |
| Priority date | — |
| Expiry date | Apr 17, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electronic system such as a Single-Chip-Module (SCM), a Multi-Chip-Module (MCM), or a Board-Level-Product (BLP) includes a plurality of units which are interconnected by a terminated transmission bus line. Each unit includes a CMOS circuit, a terminated bus line for signal transmission, and a driver/receiver circuit which is spaced from the CMOS circuit on a substrate. A guard ring is formed around at least a part of the CMOS circuit which faces the driver/receiver circuit. The driver/receiver circuit includes a driver for receiving an input logic signal from the CMOS circuit and inducing a corresponding signal onto the bus line, and a receiver for receiving an output signal from the bus line and providing a corresponding output logic signal to the CMOS circuit. The receiver includes a receiver transistor having a gate electrically connected to the bus line and producing a current in relation to the received signal, a comparator for comparing a voltage level of the received signal to a reference voltage level and for splitting the current into a first path having a current inversely proportional to the received signal and a second path having a current in proportion to the recei…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.