Charge pump for phase lock loop
US5576647A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 1995 |
| Grant date | Nov 19, 1996 |
| Priority date | — |
| Expiry date | Jun 22, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0995
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A monolithic CMOS phase-lock loop (PLL) circuit provides a high frequency of operation suitable for RF applications. The PLL produces an output clock with high spectral purity and very low jitter. The output clock has a low static phase error relative to a reference input, making the PLL also useful for clock synchronizing applications, such as clock recovery elements in transmission/recording channels. The PLL provides in-phase and quadrature signals from a VCO which has two differential transconductor stages having negative output conductance. The PLL also includes a charge pump using transistors driven by high speed switching drivers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.