Discrete time digital phase locked loop
US5576664A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 1995 |
| Grant date | Nov 19, 1996 |
| Priority date | — |
| Expiry date | Nov 2, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/181
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A communication receiver (100) employs a discrete time digital phase locked loop (142) for maintaining a generated signal (144) locked to a reference signal (136). The discrete time digital phase locked loop (142) includes a phase detector (202), an accumulator (219), an adder (227), and a controlled oscillator (232). The accumulator (219) is connected to the phase detector (202) and a reference signal (136) for calculating an accumulator output value equal to a first sum of a current sample generated by the phase detector (202), and all of the plurality of discrete phase error samples produced prior to the current sample. The adder (227) is connected to the phase detector (202) and the accumulator (219) for forming a second sum of the current sample and the accumulator output value. The controlled oscillator (232) receives the second sum, which is utilized for controlling the controlled oscillator (232).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.