Secure non-volatile memory array
US5576988A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 1995 |
| Grant date | Nov 19, 1996 |
| Priority date | — |
| Expiry date | Apr 27, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/922
Abstract
An improved EEPROM structure is disclosed which provides protection against external detection of data stored within the array's memory cells via microprobing by causing the array's word lines to de-activate upon an attempted deprocessing of the array. An EEPROM "protect" cell is connected in parallel between each word line within the array and ground potential. Each of these protect cells has formed therein one or more substantially vertical cavities filled with a high etching film. These cavities are provided in a region adjacent to an end of the protect cell's floating gate such that during an attempted deprocessing of the array using an etching process in order to expose the array's word, bit, and control lines for microprobing, the etchant will rapidly diffuse through these cavities, exposing and discharging the floating gate before fully exposing the word, bit, and control lines. Once discharged, each protect cell shorts its associated word line to ground potential. Holding the word lines at ground potential in such a manner precludes the activation of the word lines and, therefore, effectively prevents the external reading of data stored within the array via microprobing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.