Memory system and method
US5577004A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 1, 1995 |
| Grant date | Nov 19, 1996 |
| Priority date | — |
| Expiry date | Dec 1, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system wherein a plurality of memory banks is provided, each having a plurality of addressable memory units. A driver is coupled to a set of address terminals of a corresponding one of the memory units in each one of the memory banks. Each bit of data is fed to a data terminal of a corresponding one of the memory units in each one of the memory banks. An error detection and correction (EDAC) unit is fed by the data passing to, or from, the memory system. With such an arrangement, a failure of any one of the drivers results in an error in only one bit of the data stored in the incorrectly addressed location, and such single bit error is corrected by the EDAC unit upon its retrieval from the memory system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.