Scan based testing for analogue circuitry
US5577052A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Nov 19, 1996 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318536
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit containing analogue operation circuitry having a plurality of nodes for input and output of signals during normal operation, a plurality of scan cells connected to at least said plurality of nodes for containing signals to be utilized in selected tests to be performed on said analogue operation circuitry and responsive to selected output signals is provided. A method for testing a module of analogue circuitry incorporated into an integrated circuit having other circuitry by decoupling a plurality of module signal terminals from respective normal operation connections to a plurality of scan cells, and inputting at least portions of test suites and sensing test result output signals through at least selected ones of said scan cells is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.