Combined clock recovery/frequency stabilization loop
US5577074A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 1995 |
| Grant date | Nov 19, 1996 |
| Priority date | — |
| Expiry date | Oct 20, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0079
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The effects of long-term drift in a local reference oscillator are compensated by dividing the local reference oscillator frequency by one of three divider patterns (nominal ratio, add a cycle, delete a cycle) so that the symbol clock of the remote terminal is equal to the outroute symbol rate. The number of add a cycle and delete a cycle divider patterns are counted and stored. The average of the number of add a cycle and delete a cycle patterns is used to control the transmit frequency of the remote terminal to correspond to the outroute symbol rate. Thus, the clock recovery process generates a frequency calibration number used to track the frequency of the remote terminal local reference oscillator and to adjust the transmit frequency of the remote terminal accordingly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.