Edge detector
US5577078A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 1995 |
| Grant date | Nov 19, 1996 |
| Priority date | — |
| Expiry date | May 26, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0338
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An edge detector has a digital phase locking loop in which one of the signals (e.g., the data signal) is coupled to a delay chain that develops a series of incrementally phase delayed versions of the input. Adjacent phase delayed pairs are selected, one pair at a time, and are compared to the other signal (e.g., the clock signal) to determine if an edge of the clock falls between the edges of the data signal in the selected phase pair, or falls outside the edges of the selected phase pair, on one side or the other thereof. If the clock edge falls outside the selected pair, a control signal selects another pair for comparison and the process is repeated until, for example, the data edges are aligned with the positive going edge of the clock. With a clock frequency equal to twice data frequency, the data can then be sampled on the falling edge of the clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.