Method and apparatus for preforming memory segment limit violation checks
US5577219A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 1994 |
| Grant date | Nov 19, 1996 |
| Priority date | — |
| Expiry date | May 2, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for determining if an effective address for a memory access in a computer processor is above an expand-down memory segment. The apparatus comprises a memory segment limit comparison circuit. The segment limit comparison circuit tests every memory access to determine if the memory access reaches above the top limit of an expand-down memory segment. The comparison circuit consists of an adder that adds an effective address of the memory access to an access.sub.-- size value. The access.sub.-- size value consists of the size of the memory access to be performed minus one in the low order bits and a series of "1" bits in the high order bits necessary to generate a carry if the memory access reaches above the top limit of the expand-down memory segment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.