Dynamic random access memory (DRAM) with cache and tag
US5577223A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 1994 |
| Grant date | Nov 19, 1996 |
| Priority date | — |
| Expiry date | Aug 29, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0893
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic RAM having a TAG address holding circuit in a TAG block in correspondence with one of a plurality of sub-arrays to hold the lower bits of an X (row) address. A block control circuit in the TAG block determines a "Hit" or "Miss" in accordance with the held address and a new X address in response to the sub-address and outputs a TAG determination signal. In response to the TAG judgment signal, a sub-array control circuit transfers a signal for access to the TAG block and a column sense amplifier. The column sense amplifier is utilized as a cache and data latched in the column sense amplifier are read out on a data bus when a "Hit" is determined.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.