Multistage timing circuit having multiple counters in each timer for generating programmable duration output signals without any delay
US5577238A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 1996 |
| Grant date | Nov 19, 1996 |
| Priority date | — |
| Expiry date | Mar 22, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05B19/045
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
The auto-sequenced state machine according to the present invention has a programmable state duration which is independent from the logic speed, it may be adapted to any Moore state machine and may operate in metastability occurrence of the latches (2) of the state machine. The programming of a granularity of half a clock cycle provides a performance optimization by using a system of two clocks which are in opposite phase. Moreover, the state duration may be programmable on line. The auto-sequenced state machine is composed of a basic Moore state machine to which is connected a device (16) comprising a current state decoder (15) which decodes the current state signals Q(t) from the Moore state machine in order to select one of the biphase state timers (13) and one of the state timing programming circuits (12), and an OR circuit (11) which receives the terminal counts (TC0, . . . , TC3) issued from the current selected biphase state timer and generates the final current terminal count (7) to the latches (2) of Moore state machine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.