Instruction processor control system using separate hardware and microcode control signals to control the pipelined execution of multiple classes of machine instructions
US5577259A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 1994 |
| Grant date | Nov 19, 1996 |
| Priority date | — |
| Expiry date | Aug 9, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital instruction processor control system for an instruction processor having a multiple stage instruction execution pipeline capable of executing binary instructions in fixed predetermined stages. The control system includes a hardware controller to generate control signals for execution of all pipeline stages of standard instructions and for the first stage of extended cycle instructions and provides a main microcode controller to provide programmed control signals for controlling all subsequent stages of execution of extended cycle instructions. The control system also utilizes a separate sequence microcode controller for execution of certain instructions of a predetermined type including decimal instruction execution, during which time the main microcode controller is under control of the separate sequence controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.