Method of fabricating improved lateral Silicon-On-Insulator (SOI) power device
US5578506A · kind A · utility
5Cited by
8References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 27, 1995 |
| Grant date | Nov 26, 1996 |
| Priority date | — |
| Expiry date | Feb 27, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6717
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high performance lateral Silicon-On-Insulator (SOI) power device having a high breakdown voltage (.ltoreq.100 v). The SOI power device includes a silicon layer formed on an oxide layer over a silicon substrate. A mask having a single opening on the anode (drain) side of the silicon layer is formed thereon such that an impurity may be introduced into the silicon layer. The resultant dopant is implanted in the anode side and laterally diffused by high temperature annealing. The resultant device sustains breakdown voltages of up to 100 volts and enables an extremely low on-state resistance of 1.2 milliohm-cm.sup.2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.