Dynamic semiconductor memory device with higher density bit line/word line layout
US5578847A · kind A · utility
16Cited by
7References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 13, 1995 |
| Grant date | Nov 26, 1996 |
| Priority date | — |
| Expiry date | Mar 13, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/907
Abstract
A plurality of bit line contacts provided on one bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL and a plurality of bit line contacts provided on an adjacent bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL which is different from the space in which a corresponding one of the bit line contacts formed on the former bit line is arranged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.