Circuit for limiting the maximum current value supplied to a load by a power MOS at power-up
US5578956A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 1996 |
| Grant date | Nov 26, 1996 |
| Priority date | — |
| Expiry date | Mar 14, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/0822
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention concerns a circuit for limiting the maximum current to be supplied to a load through a power MOS, being an improvement of the limiting circuitry which uses an equalizing capacitor. The addition of circuitry with a one-way current flow between a terminal of the equalizing capacitor and the gate terminal of the power MOS is effective to lower the voltage across the capacitor and to speed up its charging process, thereby making the current limiting action expected from the circuit a timely one. The circuitry which limits current flow to one direction may include a second MOS of the same type as the power MOS. In this way, any deviations of the power MOS from its designed operation, e.g. due to its manufacturing process variation and thermal drift phenomena, can also be compensated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.