Computer multiply instruction with a subresult selection option
US5579253A · kind A · utility
Inventors
Key dates
| Filing date | Sep 2, 1994 |
| Grant date | Nov 26, 1996 |
| Priority date | — |
| Expiry date | Sep 2, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/523
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A N-bit by N-bit multiplication apparatus having the ability to select a part of the multiplication result for storage into a result register N-bits wide. A first embodiment of the invention allows a sequence of n-bits from the N-bit by N-bit multiply result to be stored into an N-bit wide register. N+1 to 1 multiplexors are utilized to select which of the multiply result bits are stored into the result register in response to a computer instruction. The second preferred embodiment utilizes multiplexors having fewer than N+1 inputs to select discrete subsets of the multiply result bits for storage into the N-bit wide result register. In this manner, less complex multiplexors are required which take less chip area to implement. The third preferred embodiment utilizes multiple sets of multiplexors to select multiple subresults generated by a parallel multiplication operation. The multiple subresults are stored in a single result register. By allowing subresults to be selected and stored as part of the multiply operation, a multiply apparatus according to the present invention is more time and instruction efficient than prior art devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.