Program verify and erase verify control circuit for EPROM/flash
US5579262A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 5, 1996 |
| Grant date | Nov 26, 1996 |
| Priority date | — |
| Expiry date | Feb 5, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A program verify and erase verify control circuit is disclosed for use with an EEPROM/flash memory system wherein each memory cell can be read, erased or programmed based, in part, on the voltage level of a word line coupled to the gate of each of the memory cells. Program operations are verified by placing a worst case (i.e., highest) read voltage on the word lines of programmed memory cells. Similarly, erase operations are verified by placing a worst case (i.e., lowest) read voltage on the word lines of erased memory cells. So that there worst case voltages are stable and reproducible, they are generated using a feedback control circuit consisting of a comparator driven by a bandgap voltage reference (+1.28 VDC ), various feedback transistors and a voltage divider network. The worst case program verification voltage (+6.4 VDC) and the worst case erase verification voltage (+4.0 VDC) are selectively generated by the disclosed circuitry in response to program verify (PV) and erase verify (EV) signals generated by the host computer in which the memory system is installed. The host issues these signals, which initiate a verification operation, following each erase or program operatio…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.