Test circuitry for printer memory
US5579477A · kind A · utility
7Cited by
4References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 15, 1996 |
| Grant date | Nov 26, 1996 |
| Priority date | — |
| Expiry date | Mar 15, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A printer has test circuitry external to its processor to test memories used inside the printer. The test is initiated by the processor by signalling the test circuitry. The test circuitry stores a first sequence in each memory then reads the sequence from the memory and compares the memory's data to the original sequence. The test is repeated with a second sequence which is the logical inverse of the first sequence. If an error occurs, a flag is set. When the test is complete, the processor is notified. The processor can check the error flag to determine whether the test was successful.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.