Control apparatus for controlling data read accesses to memory and subsequent address generation scheme based on data/memory width determination and address validation
US5579500A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 1994 |
| Grant date | Nov 26, 1996 |
| Priority date | — |
| Expiry date | Feb 23, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for controlling data read access to memory, in response to an access request sent through a system bus. The apparatus includes an data storage device for preserving data corresponding to a predetermined address; a judging device for judging whether an access address indicated by the access request matches the predetermined address; and a control device for making the data storage device output data preserved therein to the system bus when the access address has been judged to match the predetermined address, and for making the data storage device hold data corresponding to a next address subsequent to the access address when the access address has been judged not to match the predetermined address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.