FET and/or bipolar devices formed in thin vertical silicon on insulator (SOI) structures

US5581101A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Tak H. Ning · Yorktown Heights, US
• Ben Wu · Shanghai, CN

Key dates

• Filing date: Jan 3, 1995
• Grant date: Dec 3, 1996
• Expiry date: Jan 3, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

A process for fabricating Ultra Large Scale Integrated (ULSI) circuits in Silicon On Insulator (SOI) technology in which the device structures, which can be bipolar, FET, or a combination, are formed in vertical silicon sidewalls having insulation under and in back thereof so as to create SKI device structures. The silicon sidewall device SOI structures, when fabricated, take the form of cells with each cell having a plurality of either bipolar devices, FET devices, or a combination of these devices, such as collectors, emitters, bases, sources, drains, and gates interconnected within the planes of the regions of the devices in the cells and can be interconnected within the planes of the regions of devices in adjacent cells. Further, the interconnections to adjacent cells can be made from the back of the silicon sidewalls.