Digital signal comparison circuit in a performance monitoring and test system
US5581228A · kind A · utility
34Cited by
5References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 26, 1995 |
| Grant date | Dec 3, 1996 |
| Priority date | — |
| Expiry date | May 26, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M3/244
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A DS3 level access, monitor and test system including a digital comparator for a telephone network. A high speed bit-for-bit compare is interfaced to a protect path to provide 1:1 fault protection in the system of the present invention. Full time performance monitoring on DS1 and DS3 signals is performed by a shared resource. The system of the present invention provides an integrated approach to synchronization measurement and relative synchronization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.