Architecture for a high definition video frame memory and an accompanying data organization for use therewith and efficient access therefrom
US5581310A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 1995 |
| Grant date | Dec 3, 1996 |
| Priority date | — |
| Expiry date | Jan 26, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/61
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An architecture for a memory with a wide word, e.g. n-byte, width particularly suited for use as a high definition video frame store memory (80), and an accompanying organization for storing pixel data therein to facilitate efficient block and raster access therefrom. Specifically, the memory relies on storing n-byte wide words (n=(m.sub.1 .times.m.sub.2)) across m.sub.2 independent m.sub.1 -byte wide memory segments, with pre-defined positional offsets between respective m.sub.1 -byte words (203)("nibbles") stored in successive memory segments. All these segments are simultaneously accessed on a read or write basis. During a memory write operation, all the nibbles in an n-byte wide input word are appropriately shuffled to yield the proper inter-segment offsets prior to being written into the memory as a collective n-byte memory write word. During a read operation, all the nibbles read from memory in a collective n-byte memory read word are appropriately shuffled to yield an n-byte output word. Inasmuch as either a scan line or sub-block (210.sub.W, 210.sub.X, 210.sub.Y, 210.sub.Z) of a macroblock of pixel data is collectively written to or read from the memory during one memory wr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.