Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein
US5581503A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jul 31, 1995 |
| Grant date | Dec 3, 1996 |
| Priority date | — |
| Expiry date | Jul 31, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically rewritable flash memory device which has a memory cell array arranged in rows and columns of memory cells and which is divided into a plurality of memory blocks having different memory capacities. Each memory block having one or more rows of memory cells. A common voltage control circuit is provided for each of the memory blocks for applying a first potential to a common conductor for a memory block containing a memory cell selected with a selection voltage applied to its associated data line conductor for a writing operation and a second potential higher than the first potential to a common conductor for a memory block containing a memory cell unselected with the selection voltage applied to its associated data line conductor and containing no selected memory cell for a writing operation. A microcomputer having a CPU and the above-mentioned electrically rewritable flash memory formed in a single semiconductor chip includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of the CPU and a second operation mode in which the flash memory is rewri…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.