Semiconductor memory having sub-word line replacement
US5581508A · kind A · utility
25Cited by
5References
4Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 9, 1994 |
| Grant date | Dec 3, 1996 |
| Priority date | — |
| Expiry date | Dec 9, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory apparatus having a row decoder classified by main word lines and word lines, the number of spare lines for a defect is increased without increasing the number of spare main word lines. The area of a redundancy circuit is minimized to improve the yield of chip. Normal and spare memory blocks each including a plurality of memory cells are each divided so that replacement may be effected without increasing the number of spare main word lines even when defective addresses associated with a plurality of normal main word lines take place.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.