Device for and method of counting bit errors and device for and method of identifying signals
US5581577A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 16, 1994 |
| Grant date | Dec 3, 1996 |
| Priority date | — |
| Expiry date | Feb 16, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A bit error counter for a digital communication system has transmitter and receiver. The transmitter includes circuitry for convolution encoding of an input original signal and outputting a transmission signal. The receiver includes error correcting/decoding circuitry for inputting a reception signal corresponding to the transmission signal and outputting a decoded signal, and when an overflow occurs, for outputting an overflow signal. State monitoring circuitry is provided for receiving the overflow signal and issuing a switching instruction signal to a switch only when the overflow signal is received. The switch also receives the decoded signal and outputs at least one of a bit error rate or a number of errors when the switching instruction signal is received. The switch outputs the decoded signal when the switching instruction signal is not received. Re-encoding circuitry receives the decoded signal from the switch and outputs a re-encoded signal by subjecting the decoded signal to the same encoding as that of the reception signal. A comparator receives the re-encoded signal and a delayed reception signal, and outputs the bit error rate and the number of errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.