Signal processing apparatus including plural aggregates
US5581662A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 1995 |
| Grant date | Dec 3, 1996 |
| Priority date | — |
| Expiry date | May 15, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hierarchical signal processing apparatus includes aggregates having logic operation portions. The apparatus compares a final output signal from a logic operation portion in a final aggregate with a teaching signal, and generates an error signal by taking a signal which exists only in the teaching signal as a positive error signal, and taking a signal which exists only in said final output signal as a negative error signal. An error signal generating portion in the apparatus generates a positive error signal of a logic operating portion within a certain aggregate which supplies one or more output signals thereof to said logic operation means of another aggregate based on one or more logic operations on the excitatory weight function signal of said weight function signal, the positive error signal, the inhibitory weight function signal of said weight function signal and the negative error signal, and also generates a negative error signal of said logic operation means within said certain aggregate which supplies one or more output signals thereof to said logic operation means of said other aggregate based on one or more logic operations on the inhibitory weight function signal of s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.