Process to form rugged polycrystalline silicon surfaces
US5583070A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 1995 |
| Grant date | Dec 10, 1996 |
| Priority date | — |
| Expiry date | Jul 7, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/964
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating stacked capacitor, DRAM, devices, has been developed in which the surface area of the storage node has been significantly increased as a result of a unique set of deposition and annealing conditions. An amorphous polysilicon layer, used as the upper layer of the storage node, is ramped up in pure nitrogen, and then insitu annealed, to result in a polycrystalline structure, exhibiting significant surface area increases, due to the formation of surface concave and convex protrusions. The increase in storage node surface area allows for increased DRAM capacitance, without the use of larger dimension stacked capacitors, or thinner dielectrics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.