Digital-to-analog converter with digital linearity correction
US5583501A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 1994 |
| Grant date | Dec 10, 1996 |
| Priority date | — |
| Expiry date | Aug 24, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Digital linearity correction is obtained by generating a digital calibration signal having at least one frequency component, converting the digital calibration signal to an analog signal, and detecting distortion in the analog signal generated from the calibration signal by nonlinearity to produce a compensation coefficient used to digitally compensate the digital input of the digital-to-analog converter. The compensation coefficient is adjusted in a feedback loop so that the distortion is minimized. Preferably the calibration signal has two frequencies, and the distortion is an intermodulation component having a substantially lower frequency. The intermodulation component, for example, is selected by an R-C low-pass filter, digitized by an analog-to-digital converter, and detected by digital signal processing. The analog-to-digital converter may have low resolution, low dynamic range and a low sampling rate. Preferably the digital compensation includes computing a third-order polynomial, and the intermodulation components for the second and third order terms are detected at about the same frequency. Preferably the offset of the digital-to-analog converter is calibrated first by se…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.