Semiconductor memory capable of reducing erase time
US5583809A · kind A · utility
13Cited by
5References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 12, 1995 |
| Grant date | Dec 10, 1996 |
| Priority date | — |
| Expiry date | May 12, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory comprising an erase pulse generator, an erase pulse counter and an erase verify signal generator. The erase pulse counter counts erase pulses output by the erase pulse generator, and the erase verify signal generator generates an erase verify signal. The erase pulse counter keeps the erase verify signal generator inactive until the number of the counted erase pulses exceeds a predetermined count. Only erase operations are allowed to continue while erase verify operations are being suppressed, until the erase pulse count exceeds the predetermined count. The scheme shortens the erase time involved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.