Storage cell using low powered/low threshold CMOS pass transistors having reduced charge leakage
US5583821A · kind A · utility
23Cited by
2References
23Claims
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Assignee
Inventors
Key dates
| Filing date | Jul 31, 1995 |
| Grant date | Dec 10, 1996 |
| Priority date | — |
| Expiry date | Jul 31, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage cell includes a first bit line, a storage circuit, and a pass transistor. The storage circuit has a first storage node for holding a logic state indicative of a logic value. The pass transistor is coupled to the first bit line and the first storage node for establishing a conduction path therebetween. The pass transistor receives a bias voltage to switch the pass transistor into a substantially nonconducting state when the storage cell is not being accessed. The reverse bias on the first transistor substantially reduces the leakage current through the pass transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.