Dram refresh circuit
US5583823A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 1, 1995 |
| Grant date | Dec 10, 1996 |
| Priority date | — |
| Expiry date | Dec 1, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM refresh circuit includes control logic for selectively placing the DRAM in normal modes of operation. An X register stores and outputs the capacity value of a DRAM, and a timer receives the output value of a timer register and a timer clock, and counts a refresh operation time. A refresh counter receives the output of a refresh counter register and a refresh counter clock, and counts the refresh operations. A comparator compares the output signals of the refresh counter, timer, and X register, and outputs a refresh enable signal in response to these signals. A priority circuit receives the output signals of the control logic and comparator and generates signals corresponding to the normal modes of operation and the refresh mode. A memory control signal generator is also provided for generating RASI and CASI signals and the refresh counter clock in accordance with the output from priority circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.