Virtual memory address translation apparatus and method using link, auxiliary link and page tables
US5584005A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 1993 |
| Grant date | Dec 10, 1996 |
| Priority date | — |
| Expiry date | Sep 20, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0292
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method and apparatus for address translation for translating a 64-bit virtual address into a real address, the 64-bit virtual address comprises a segment number, a page index and a page offset. When this virtual address is translated into a real address, high order bits of the segment number are first input to a hash generation circuit to obtain a hash address of a link table, and this link table is retrieved by an address obtained by adding lower order bits of the segment number as an offset to obtain tag information of the virtual address and a base address of a page table. Next, the tag information of the virtual address obtained in this manner is compared with the original segment number, and the base address of the page table is judged as correct when they coincide with each other. The page table is retrieved by an address obtained by adding a page index as an offset to this base address to obtain a page frame number, and the real address is obtained by combining the original page offset with the page frame number. According to this construction, address translation can be carried out at a higher speed while maintaining compatibility with the 32-bit virtual address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.