Semiconductor integrated circuit device
US5585664A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 6, 1996 |
| Grant date | Dec 17, 1996 |
| Priority date | — |
| Expiry date | Feb 6, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Protection lines are arranged on both sides of and above a signal line, and ground lines are formed outside the protection lines and a ground line is formed above the protection line. A bias circuit is connected to the signal line and protection lines to set the potential of the protection lines equal to that of the signal line and set the impedance of the protection lines low. The signal line processing a small signal, is surrounded by the low-impedance protection lines of the same potential as that of the signal line, and thus crosstalk can be prevented from occurring between the lines, without causing the components of a high-frequency analog signal to attenuate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.