Impedance emulator
US5585741A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 19, 1995 |
| Grant date | Dec 17, 1996 |
| Priority date | — |
| Expiry date | Apr 19, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/56
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A low capacitance impedance emulator suitable for active conductor termination. The impedance emulator includes an emulating FET and a control circuit coupled to the gate of the emulating FET for maintaining the FET in a linear region of operation. The control circuit includes a control FET, an impedance setting resistor, and an amplifier. The control FET is driven in a closed-loop fashion so that the impedance of the control FET has a known relationship with respect to that of the resistor. The output of the amplifier controls the conduction of both the emulating and control FETs so that the emulating FET provides an impedance proportional to that of the control FET and thus, related to the impedance of the resistor. A disconnect feature is provided, whereby the impedance emulator is responsive to a disconnect signal for disconnecting the impedance provided by the emulating FET. The impedance provided by the emulating FET is selectable by adjusting the impedance setting resistor or, in one embodiment, the impedance is selectable in response to an impedance selection signal which causes one of a plurality of FETs to operate as the emulating FET. An NMOS FET having features providin…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.