Method for generating test vectors for characterizing and verifying the operation of integrated circuits
US5586125A · kind A · utility
Inventor
Key dates
| Filing date | Nov 22, 1994 |
| Grant date | Dec 17, 1996 |
| Priority date | — |
| Expiry date | Nov 22, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318371
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention is a method for operating a data processing system to generate a sequence of test states containing a predetermined set of states and/or transitions for use in testing an integrated circuit or the like. The method minimizes the number of additional states and/or transitions contained in the test sequence while preserving any constraints on the sequence of transitions that may be applied to the circuit to be tested. The present invention operates by defining a graph containing the predetermined set of states and/or transitions. The states are the vertices of the graph and the transitions are edges of the graph. The graph is then augmented if needed with additional states and/or transitions. The additional states and/or transitions assure the existence of an Eulerian Path through the graph. The additional states assure that the graph is connected, and that each vertex in the graph, with the possible exception of two vertices, has the same number of inbound and outgoing transitions. The Eulerian Path is then traced to provide a sequence of states that includes the input list of states and/or transitions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.