High speed segmented neural network and fabrication method
US5586223A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 1995 |
| Grant date | Dec 17, 1996 |
| Priority date | — |
| Expiry date | Feb 15, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/09
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high speed, feed forward, segmented neural network and fabrication technique are described. The segmented network includes a plurality of network layers stacked in an ascending pyramid fashion. The network layers are structured with a plurality of subnetworks, and within each subnetwork exists a plurality of nodes structured in a fully interconnected and/or partially interconnected layered neural network arrangement. The inputs and outputs of each subnetwork are one bit digital values constrained to `0` or `1`, while any number of nodes with any number of layers may be modeled for each subnetwork. Each subnetwork is independent of all other subnetworks in a given network layer, and thus, each network layer is segmented. In hardware implementation, each subnetwork comprises a simple memory device, such as a RAM or PROM look-up table. The speed of the neural network system is high and largely dictated by the access time of the memory devices used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.