Method and apparatus for validating I/O addresses in a fault-tolerant computer system
US5586253A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1994 |
| Grant date | Dec 17, 1996 |
| Priority date | — |
| Expiry date | Dec 15, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/141
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel mapping and protection circuit arrangement comprises a plurality of checking mechanisms that collectively cooperate to verify the accuracy of I/O addresses generated by input/output (I/O) controllers of a fault-tolerant computer. These verified I/O addresses are translated into system addresses to enable direct memory access (DMA) transactions between the controllers and the computer's host memory. Specifically, certain of the checking mechanisms cooperate to ensure that the DMA accesses are directed to correct pages in host memory, while other checking mechanisms are provided to ensure that memory access operations are performed at correct locations within the page. Additional checking mechanisms are provided to further verify the accuracy of generated I/O addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.