Atomic operation control scheme
US5586274A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 1994 |
| Grant date | Dec 17, 1996 |
| Priority date | — |
| Expiry date | Mar 24, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A split transaction bus system that accommodates atomic operations without locking the bus and without the possibility of deadlock during the atomic operations. The bus system may be used in a computer system that includes a bus, component modules that send transactions to each other on the bus, and a bus controller that limits the types of transactions that can be sent on the bus at any given time. When one module is performing an atomic operation, the bus controller limits transactions to those that do not change the memory image that existed when the atomic operation was commenced. The bus controller, however, permits responses or returns of data, assuming the response or return does not alter the current value of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.