Memory system employing pipeline process for accessing memory banks
US5586282A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 1994 |
| Grant date | Dec 17, 1996 |
| Priority date | — |
| Expiry date | Nov 14, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory access system employs a pipe-line process in which access can be carried out for a microprocessor using one cycle of two clocks and for a microprocessor using one cycle of one clock. Access speed of a main memory can be considerably improved ensuring applicability in general use. A transition request signal to a pipe-line is received, a control signal that continues as long as the cycle number corresponding to at least the address first-out number of the pipe-line immediately after the start of the pipe-line operation is produced. Concurrently, a data complete signal indicating the completion of data access for a bank is produced during the time that either of the above two signals is also generating an address latch signal synchronized to a clock signal and routed to respective banks, for executing high speed data access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.