Power management for low power processors through the use of auto clock-throttling
US5586332A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 1993 |
| Grant date | Dec 17, 1996 |
| Priority date | — |
| Expiry date | Mar 24, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock throttling mechanism turns off certain processor components to minimize power consumption. The processor detects the issuance of certain bus cycles or the execution of certain instructions which typically cause the processor to be idle for a period of time. Control circuitry detects the existence of the instruction and/or bus cycle and shuts down the clock driving certain processor components during that idle period. The control circuitry then detects the occurrence or upcoming occurrence of an event to which the processor responds and becomes active. At detection of this event, the clock signal input to these components is then restarted such that the processor can continue normal execution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.