Bipolar transistor and manufacturing method
US5587599A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 1995 |
| Grant date | Dec 24, 1996 |
| Priority date | — |
| Expiry date | May 23, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
Abstract
Bipolar transistor, potentially with monolithically integrated MOSFETs, in the body silicon layer having a thickness of approximately 0.6 .mu.m in a SOI substrate, have a collector region and a base region that are produced by implantation. An oxide layer provided for the gate oxide of the MOSFETs is applied surface-wide and is partially removed in the region of the bipolar transistor, a polysilicon layer (5) also employed for the gate electrodes of the MOSFETs is applied and structured. Implantation for highly doped termination regions (5, 10, 12) for emitter, base and collector ensue with masks (13). An emitter region (8) is driven out of the highly doped polysilicon layer as terminal region for the emitter in a temperature step. The doping degree of the collector region, as lowest doped region, can be selected so light that the collector region is completely depleted. The function corresponds to a vertical bipolar transistor with a lateral collector space-charged zone.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.