Two-transistor zero-power electrically-alterable non-volatile latch
US5587603A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 6, 1995 |
| Grant date | Dec 24, 1996 |
| Priority date | — |
| Expiry date | Jan 6, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A two-transistor, zero-power, electrically-alterable non-volatile latch element comprises an input node, an output node, and an erase node. A P-Channel MOS transistor has a source connected to a source of first electrical potential, a drain connected to the output node, a control gate connected to the input node, and a floating gate capacitively coupled to the control gate. An N-Channel MOS transistor has a source connected to a source of second electrical potential lower than the first electrical potential, a drain connected to the output node, a control gate connected to the input node, and a floating gate capacitively coupled to the control gate and electrically connected to the floating gate of the P-Channel MOS transistor. The floating gates of the P-Channel MOS transistor and the N-Channel MOS transistor are capacitively coupled to the erase node via a tunnel dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.