Four-quadrant biCMOS analog multiplier
US5587682A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 1995 |
| Grant date | Dec 24, 1996 |
| Priority date | — |
| Expiry date | Mar 30, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06G7/163
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An analog multiplier circuit includes three transconductance stages. One of the transconductance stages, receiving a first differential voltage, conducts a differential current responsive to the first differential voltage from the other two transconductance stages. The differential current changes the transconductance in the other two transconductance stages, which are cross-coupled with one another. The second differential input voltage is presented to the other two transconductance stages in parallel, resulting in an output differential current or voltage based on the product of the first and second differential input voltages. Each of the transconductance stages is implemented in BiCMOS, and each includes two differential legs, each having a MOS transistor receiving an input signal and a cascode bipolar transistor. Each transconductance stage also includes a reference leg which develops the drain-source voltage for the MOS transistors; the first transconductance stage differentially varies this drain-source voltage in the other two stages to produce the product.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.