High density multistate SRAM and cell
US5587944A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 1996 |
| Grant date | Dec 24, 1996 |
| Priority date | — |
| Expiry date | Mar 18, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5614
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high density multistate SRAM cell including N negative differential resistance diodes connected in series and to a load. The diodes and the load defining a memory node having N+1 stable states. A write transistor having a drain connected to the memory node and adapted to receive N+1 different amplitudes of voltage on the source, and a write signal on the gate. An amplifier having an input terminal connected to the memory node, and a read switch having an input terminal connected to the output terminal of the amplifier. A plurality of cells connected into a matrix with N+1 sense amplifiers associated with each column of the matrix so as to provide an output for each of the N+1 different amplitudes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.