Post-processing bit-map decimation compensation method for printing high quality images
US5588094A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 3, 1994 |
| Grant date | Dec 24, 1996 |
| Priority date | — |
| Expiry date | Jan 3, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N1/40025
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A digital halftone pattern geometry adapted not to the characteristics of variable dot size printing presses but to the operating characteristics of the printer itself achieves a high degree of image quality. Techniques for creating the halftone pattern geometry include linear spot growth to provide uniform darkening and the use of a super-cell structure to maximize the number of tint or gray scale levels. A preferred super-cell structure is of hexagonal dispersed-dot form to reduce low frequency artifacts by spreading them over a greater number of frequencies. An increase in addressability to enhance printer resolution in the direction of the path of print medium travel with no change in dot size will cause placement of overlapping dots when a darkening of consecutive pixels in the direction of print medium travel is called for in the halftone pattern. Post-processing bit-map decimation compensation on bit map image data just before they are transmitted to the printer for printing reduces excessive dot overlap but maintains edge information. The removal from the bit map data corresponding to obscured dots renders nonoverlapping dots occupying a region of the same size as that if n…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.